VLSI Design. DC & Transient Response. EE 447 VLSI Design 4: DC and Transient Response 1

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1 VLSI Design DC & Transient Response 4: DC and Transient Response 1

2 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation 4: DC and Transient Response

3 DC Response DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 -> V out = When V in = -> V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations V in But graphical solution gives more insight I dsp I dsn V out 4: DC and Transient Response 3

4 Transistor Operation Current depends on region of transistor behavior For what V in and V out are nmos and pmos in Cutoff? Linear? Saturation? 4: DC and Transient Response 4

5 I-V Characteristics Make pmos is wider than nmos such that β n = β p V gsn5 I dsn V gsn4 V gsn3 -V dsp V gsp1 V gsp - 0 V gsn V gsn1 V gsp3 V dsn V gsp4 -I dsp V gsp5 4: DC and Transient Response 5

6 Current vs. V out, V in V in0 V in5 I dsn, I dsp V in1 V in4 V in V in3 V in3 V in4 V in V in1 V out 4: DC and Transient Response 6

7 Load Line Analysis For a given V in : Plot I dsn, I dsp vs. V out V out must be where currents are equal in V in0 V in5 I dsn, I dsp V in1 V in4 V in V in3 V in I dsp V out V in3 V in4 V in V in1 I dsn V out 4: DC and Transient Response 7

8 Load Line Analysis V in = 0 V in0 I dsn, I dsp V in0 V out 4: DC and Transient Response 8

9 Load Line Analysis V in = 0. I dsn, I dsp V in1 V in1 V out 4: DC and Transient Response 9

10 Load Line Analysis V in = 0.4 I dsn, I dsp V in V in V out 4: DC and Transient Response 10

11 Load Line Analysis V in = 0.6 I dsn, I dsp V in3 V in3 V out 4: DC and Transient Response 11

12 Load Line Analysis V in = 0.8 I dsn, I dsp V in4 V in4 V out 4: DC and Transient Response 1

13 Load Line Analysis V in = V in0 V in5 I dsn, I dsp V in1 V in V in3 V in4 V out 4: DC and Transient Response 13

14 Load Line Summary V in0 V in5 I dsn, I dsp V in1 V in4 V in V in3 V in3 V in4 V in V in1 V out 4: DC and Transient Response 14

15 DC Transfer Curve Transcribe points onto V in vs. V out plot A B V in0 V in5 V in1 V in4 V out C V in V in3 V in3 V in4 V in V in1 0 D E V tn / +V tp V out V in 4: DC and Transient Response 15

16 Operating Regions Revisit transistor operating regions Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff V out A B 0 C D E V tn / +V tp V in 4: DC and Transient Response 16

17 Beta Ratio If β p / β n 1, switching point will move from / Called skewed gate Other gates: collapse into equivalent inverter V out β p 0.1 β = n β p 10 β = n V in 4: DC and Transient Response 17

18 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L Logical Low Input Range GND 4: DC and Transient Response 18

19 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic V out Unity Gain Points Slope = -1 V OH β p /β n > 1 V in V out V OL 0 V tn V IL V IH - V tp V in 4: DC and Transient Response 19

20 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to or vice versa 4: DC and Transient Response 0

21 Inverter Step Response Ex: find step response of inverter driving load cap V in ( t) V ( t < t ) = out dv out dt = ( t) 0 = V in (t) I dsn (t) V out (t) C load 4: DC and Transient Response 1

22 Inverter Step Response Ex: find step response of inverter driving load cap V V in out () t = ( t < t ) 0 dvout () t = dt ut ( t) V = 0 DD V in (t) I dsn (t) V out (t) C load 4: DC and Transient Response

23 Inverter Step Response Ex: find step response of inverter driving load cap V V in out ( t) ( t < = ut ( t) V t 0 dvot u ( t) = dt 0 ) = V DD DD V in (t) I dsn (t) V out (t) C load 4: DC and Transient Response 3

24 Inverter Step Response Ex: find step response of inverter driving load cap V V in out () t = ut ( ( t < t ) dvo ut ( t) dt 0 = t) V 0 = V I C DD dsn DD () t load V in (t) I dsn (t) V out (t) C load t t I t V V V < V V 0 dsn () = Vout > DD t out DD t 4: DC and Transient Response 4

25 Inverter Step Response I Ex: find step response of inverter driving load cap V V in out () t = ut ( ( t < t ) dvo ut ( t) dt 0 = 0 t) V 0 = V I C DD dsn DD () t load 0 β dsn ( t) = ( VDD V) Vout > VDD Vt Vout ( t) β VDD V t V () t V < V D V out out D t t t V in (t) I dsn (t) V out (t) C load 4: DC and Transient Response 5

26 Inverter Step Response I Ex: find step response of inverter driving load cap V V in out () t = ut ( ( t < t ) dvo ut ( t) dt 0 0 = t) V 0 = V I C DD dsn DD () t load 0 β dsn ( t) = ( VDD V) Vout > VDD Vt Vout ( t) β VDD V t V () t V < V D V out out D t t t V in (t) t 0 I dsn (t) V in (t) V out (t) V out (t) C load t 4: DC and Transient Response 6

27 Delay Definitions t pdr : t pdf : t pd : t r : t f : fall time 4: DC and Transient Response 7

28 Delay Definitions t pdr : rising propagation delay From input to rising output crossing / t pdf : falling propagation delay From input to falling output crossing / t pd : average propagation delay t pd = (t pdr + t pdf )/ t r : rise time From output crossing 0. to 0.8 t f : fall time From output crossing 0.8 to 0. 4: DC and Transient Response 8

29 Delay Definitions t cdr : rising contamination delay From input to rising output crossing / t cdf : falling contamination delay From input to falling output crossing / t cd : average contamination delay t pd = (t cdr + t cdf )/ 4: DC and Transient Response 9

30 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write (V) V in t pdf = 66ps t pdr = 83ps 0.5 V out p 400p 600p 800p 1n t(s) 4: DC and Transient Response 30

31 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches 4: DC and Transient Response 31

32 RC Delay Models g Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance R, capacitance C Capacitance proportional to width Resistance inversely proportional to width d kc R/k d d k g g k g s kc kc s s s kc R/k kc kc d 4: DC and Transient Response 3

33 Example: 3-input NAND A 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) : DC and Transient Response 33

34 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance. C C C C C C C C C 3C 3C 3C C 3C 3C 3C 4: DC and Transient Response 34

35 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance. 5C 5C 5C C 3C 3C 4: DC and Transient Response 35

36 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd i to source i nodes i ( )... (... ) = R C + R + R C + + R + R + + R C R 1 R R 3 R N N N C 1 C C 3 C N 4: DC and Transient Response 36

37 Example: -input NAND Estimate worst-case rising and falling delay of -input NAND driving h identical gates. Y A B x h copies 4: DC and Transient Response 37

38 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies 4: DC and Transient Response 38

39 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R Y (6+4h)C t pdr = 4: DC and Transient Response 39

40 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R Y ( ) (6+4h)C t pdr = 6+ 4h RC 4: DC and Transient Response 40

41 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies 4: DC and Transient Response 41

42 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C t pdf = 4: DC and Transient Response 4

43 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C pdf ( )( R ) ( ) ( R R) 6 4 ( 7 4h) RC t = C + + h C + = + 4: DC and Transient Response 43

44 Delay Components Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance 4: DC and Transient Response 44

45 Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously A B x 6C C Y 4hC tcdr = 3+ h RC ( ) R R Y (6+4h)C 4: DC and Transient Response 45

46 Diffusion Capacitance we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion C C Isolated Contacted Diffusion 3 3 7C 3C 3C 3C 3C 3 3C 4: DC and Transient Response 46

47 Layout Comparison Which layout is better? A B A B Y Y GND GND 4: DC and Transient Response 47

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