Compact device - circuit macromodel specification

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1 Qucs Compact device - circuit macromodel specification A Curtice level 1 MESFET model Mike Brinson Stefan Jahn Copyright c 2007 Mike Brinson <mbrin72043@yahoo.co.uk> Copyright c 2007 Stefan Jahn <stefan@lkcc.org> Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation. A copy of the license is included in the section entitled GNU Free Documentation License.

2 Introduction The Metal and Semiconductor FET (MESFET) is a Schottky-barrier gate FET made from gallium arsenide. It is popular for high frequency applications because of it s high electron mobility. The device was developed by Walter R. Curtice 1 in 1980 at the RCA Laboratory in Princeton, New Jersey. USA. The MESFET model presented below is based on a Qucs equation defined device (EDD) which functions as a Curtice level 1 MESFET model with interelectrode capacitances. Basic temperature effects are also included. Qucs EDD model for the Curtice MESFET s Name Symbol Description Unit Default RG R G external gate resistance Ω 1m RD R D external drain resistance Ω 1m RS R S external source resistance Ω 1m VBR V DR GS breakdown voltage V LG L G external gate lead inductance H 0 LD L D external drain lead inductance H 0 LS L S external source lead inductance H 0 Is I S diode saturation current A 10f N N diode emission coefficient 1 XTI X T I diode saturation current temperature coefficient 0 EG E G diode energy gap ev 1.11 TAU τ internal time delay from drain to source s 10p RIN R IN series resistance to CGS Ω 1m CGS C GS interelectrode gate-source bias-independent F 300f capacitance CGD C GD interelectrode gate-drain bias-independent F 300f capacitance CDS C DS interelectrode drain-source bias-independent F 300f capacitance Tnom T NOM device parameter measurement temperature C 27 Temp T device temperature C 27 Alpha α coefficient of Vds in tanh function for 1/V 0.8 quadratic model 1 W.R Curtice, 1980, A MESFET model for use in the design of GaAs integrated circuits, IEEE Transactions on Microwave Theory and Techniques, MTT-28, pp

3 Name Symbol Description Unit Default Beta β transconductance parameter A/V 2 3m Lambda λ channel length modulation parameter for 1/V 40m quadratic model VTO V T O quadratic model gate threshold voltage V 6 2

4 Drain1 Num=3 Rd1 R=RD Gate1 Num=2 D1 I1=0 Q1=CGD*V1 Lg1 L=LG Rg1 R=RG Eqn2 Vt=kB/q*TK GMIe-12 TK=Temp TnK=Tnom Ld1 L=LD 1 TR=TK/TnK IsT=IS*exp(XTI/N*ln(TR) - EG/N/Vt*(1-TR)) 4 Rin1 R=RIN D2 I1=V1<-VBR+50*Vt? -IsT*(1+exp(-(VBR+V1)/Vt)) + GMIN*V1 : 0 Q1=0 I2=V1>=-VBR+50*Vt && V1<-5*Vt? -IsT+GMIN*V1 : V1>=-5*Vt? IsT*(exp(V1/(N*Vt))-1) + GMIN*V1 : 0 Q2=0 I3=V1-VT0>0? Beta*(V1-VT0)^2*(1+Lambda*V3)*tanh(Alpha*V3) : 0 Q3=CDS*V3 + TAU*I3 I4=0 Q4=CGS*V4 Source1 Num=1 Ls1 L=LS Rs1 R=RS VBR=10e10 LG=0 LD=0 LS=0 XTI=0 Temp=27 RIm Figure 1: A Qucs EDD model for the Curtice MESFET 3

5 The MESFET equations DC characteristics 1. for (V GS < V BR + 50 V T ) ( ( I GS = I S (T ) 1 + exp V )) BR + V GS + G MIN V GS (1) V T 2. for (V GS >= V BR + 50 V T ) and (V GS < 5 V T ) 3. for (V GS >= 5 V T ) I GS = I S (T ) 4. for (V GS V T O ) > 0 I GS = I S (T ) + G MIN V GS (2) ( ( ) ) VGS exp 1 + G MIN V GS (3) N V T I DS = β (V GS V T O ) 2 (1 + λ V DS ) tanh (α V DS ) (4) Where ( ) XT I I S (T ) = I S exp N ln(t R) (E G/N/V T ) (1 T R) (5) T r = T K T nk and T K = T , T nk = T NOM (6) MESFET charge equations Q GS = C GS V GS (7) Q GD = C GD V GD (8) Q DS = C DS V DS + τ I DS (9) 4

6 Test circuits and simulation results V2 U=Vgs dc simulation DC1 Id=-V1.I VBR=10 LG=0 LD=0 LS=0 XTI=0 Temp=27 RIm V1 U=Vds SW1 Sim=DC1 Param=Vds Start=-10 Stop=10 Points=41 SW2 Sim=SW1 Param=Vgs Start=-5 Stop=0 Points= Id Vds Figure 2: DC test circuit and Id-Vds characteristics 5

7 V2 U=Vgs dc simulation DC1 Id=-V1.I VBR=10 LG=0 LD=0 LS=0 XTI=0 Temp=27 RIm V1 U=Vds SW1 Sim=DC1 Param=Vgs Start=-8 Stop=0 Points=21 SW2 Sim=SW1 Param=Vds Start=1 Stop=11 Points= Id Vgs Figure 3: DC test circuit and Id-Vgs characteristics 6

8 V2 U=Vgs dc simulation DC1 Id=-V1.I Ig=-V2.I VBR=0 LG=0 LD=0 LS=0 XTI=3 Temp=Temp RIm V1 U=5 SW1 Sim=DC1 Param=Vgs Start=0.6 Stop=1.0 Points=21 SW2 Sim=SW1 Param=Temp Start=-100 Stop=+100 Points= e-3 1e-4 Ig 1e-5 1e-6 1e-7 1e-8 1e-9 1e-10 1e Vgs Figure 4: DC test circuit and Ig-Vgs characteristics 7

9 P1 Num=1 Z=50 Ohm X1 V2 U=0 dc simulation DC1 Id=-V1.I Ig=-V2.I VBR=0 LG=1p LD=5p LS=5p XTI=3 Temp=27 RIm X2 V1 U=Vds SW1 Sim=SP1 Param=Vds Start=5 Stop=20 Points=3 P2 Num=2 Z=50 Ohm S parameter simulation SP1 Start=1kHz Stop=10GHz Points=40 S[1,1] S[2,2] frequency frequency S[1,2] S[2,1] frequency frequency Figure 5: S parameter test circuit and characteristics 8