EE 447 VLSI Design. Lecture 8: Circuit Families. EE 447 VLSI Design

Transkript

1 EE 447 VLSI Design Lecture 8: Circuit Families

2 Outline Pseudo-nMOS Logic Dynamic Logic Pass Transistor Logic 2

3 Introduction What makes a circuit fast? I C dv/dt -> t pd (C/I) ΔV low capacitance high current small swing Logical effort is proportional to C/I pmos are the enemy! High capacitance for a given current B Can we take the pmos capacitance off the input? Various circuit families try to do this 4 4 3

4 Pseudo-nMOS In the old days, nmos processes had no pmos Instead, use pull-up transistor that is always ON In CMOS, use a pmos that is always ON Ratio issue Make pmos about ¼ effective strength of pulldown.8 network load P/2.2 I ds V 0.9 V out out 0.6 V in 6/2.5 P P 4 P V in 4

5 Pseudo-nMOS Gates Design for unit current on output to compare with unit inverter. pmos fights nmos inputs f Inverter NND2 NOR2 g u g avg p u p avg B g u g avg p u p avg B g u g avg p u p avg 5

6 Pseudo-nMOS Gates Design for unit current on output to compare with unit inverter. pmos fights nmos inputs f Inverter NND2 NOR2 2/3 4/3 g u g avg p u p avg B 2/3 8/3 8/3 g u g avg p u p avg 2/3 4/3 B 4/3 g u g avg p u p avg 6

7 Pseudo-nMOS Gates Design for unit current on output to compare with unit inverter. pmos fights nmos inputs f Inverter NND2 NOR2 2/3 4/3 g u 4/3 4/9 g avg 8/9 p u p avg B 2/3 8/3 8/3 g u 8/3 8/9 g avg 6/9 p u p avg 2/3 4/3 B 4/3 g u 4/3 4/9 g avg 8/9 p u p avg 7

8 Pseudo-nMOS Gates Design for unit current on output to compare with unit inverter. pmos fights nmos inputs f Inverter NND2 NOR2 2/3 4/3 g u 4/3 4/9 g avg 8/9 p u 6/3 6/9 p avg 2/9 B 2/3 8/3 8/3 g u 8/3 8/9 g avg 6/9 p u 0/3 0/9 p avg 20/9 2/3 4/3 B 4/3 g u 4/3 4/9 g avg 8/9 p u 0/3 0/9 p avg 20/9 8

9 Pseudo-nMOS Design Ex: Design a k-input ND gate using pseudo-nmos. Estimate the delay driving a fanout of H Pseudo-nMOS G F P In In k H N D 9

10 Pseudo-nMOS Design Ex: Design a k-input ND gate using pseudo-nmos. Estimate the delay driving a fanout of H G * 8/9 8/9 F GBH 8H/9 P + (4+8k)/9 (8k+3)/9 In In k Pseudo-nMOS H N 2 D NF /N + P 4 2H 8k

11 Pseudo-nMOS Power Pseudo-nMOS draws power whenever 0 Called static power P I V DD few m / gate * M gates would be a problem This is why nmos went extinct! Use pseudo-nmos sparingly for wide NORs Turn off pmos when not in use en B C

12 Dynamic Logic Dynamic gates uses a clocked pmos pullup Two modes: precharge and evaluate 2 2/3 4/3 Static Pseudo-nMOS Dynamic Precharge Evaluate Precharge 2

13 The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. precharge transistor inputs f inputs f foot footed unfooted 3

14 Logical Effort Inverter NND2 NOR2 unfooted B 2 2 B footed 3 2 B 3 2 B

15 Logical Effort Inverter NND2 NOR2 unfooted /3 2/3 B 2 2 2/3 3/3 B /3 3/3 footed 3 2 B 3 2 B 2 2/3 3/3 2 3/3 3 4/3 2 2/3 5/3 5

16 Monotonicity Dynamic gates require monotonically rising inputs during evaluation 0 -> 0 0 -> -> But not -> 0 violates monotonicity during evaluation Precharge Evaluate Precharge Output should rise but does not 6

17 Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! X Precharge Evaluate X Precharge 7

18 Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! X Precharge Evaluate X Precharge X monotonically falls during evaluation should rise but cannot 8

19 Domino Gates Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs Precharge Evaluate Precharge domino ND W W X Z X B C Z dynamic NND static inverter B W H C X H X Z B C Z 9

20 Domino Optimizations Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic S0 S S2 S3 D0 D D2 D3 H S4 S5 S6 S7 D4 D5 D6 D7 20

21 Dual-Rail Domino Domino only performs noninverting functions: ND, OR but not NND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs sig_h sig_l Meaning 0 0 Prechar ged 0 0 _l inputs f f _h 0 invalid 2

22 Example: ND/NND Given _h, _l, B_h, B_l Compute _h * B, _l ~( * B) 22

23 Example: ND/NND Given _h, _l, B_h, B_l Compute _h * B, _l ~( * B) Pulldown networks are conduction complements _l *B _h _h *B _l B_l B_h 23

24 Example: XOR/XNOR Sometimes possible to share transistors _l xnor B _h _l _l _h _h xor B B_l B_h 24

25 Leakage Dynamic node floats high during evaluation Transistors are leaky (I OFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node Must be weak enough not to fight evaluation weak keeper k X H

26 Charge Sharing Dynamic gates suffer from charge sharing B 0 x C x C x 26

27 Charge Sharing Dynamic gates suffer from charge sharing B 0 x C x C Charge sharing noise x V x V 27

28 Charge Sharing Dynamic gates suffer from charge sharing B 0 x C x C Charge sharing noise x C V V V x DD Cx + C 28

29 Secondary Precharge Solution: add secondary precharge transistors Typically need to precharge every other node Big load capacitance C helps as well x secondary precharge transistor B 29

30 Noise Sensitivity Dynamic gates are very sensitive to noise Inputs: V IH V tn Outputs: floating output susceptible noise Noise sources Capacitive crosstalk Charge sharing Power supply noise Feedthrough noise nd more! 30

31 Domino Summary Domino logic is attractive for high-speed circuits.5 2x faster than static CMOS But many challenges: Monotonicity Leakage Charge sharing Noise Widely used in high-performance microprocessors 3

32 Pass Transistor Circuits Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates CMOS + Transmission Gates: 2-input multiplexer Gates should be restoring S S B S B S S S 32

33 LEP LEn integration with Pass transistors Get rid of pmos transistors Use weak pmos feedback to pull fully high Ratio constraint S S L B 33

34 CPL Complementary Pass-transistor Logic Dual-rail form of pass transistor logic voids need for ratioed feedback Optional cross-coupling for rail-to-rail swing S S L B S S L B 34