VLSI Design I. Design for Test. Overview design for test architectures ad-hoc, scan based, built-in

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1 VLSI esign I esign for Test He s dead Jim... Overview design for test architectures ad-hoc, scan based, built-in in Goal: You are familiar with testability metrics and you know ad-hoc test structures as well as scan- based test structures. Built in test structures as BILBO and boundary scan can be applied. MicroLab, VLSI-23 (/24)

2 esign For Test What can we do to increase testability? increase observability add more pins (?!) add small probe bus, selectively enable different values onto bus use a hash function to compress a sequence of values (e.g., the values of a bus over many clock cycles) into a small number of bits for later read-out cheap read-out of all state information increase controllability use muxes to isolate sub-modules and select sources of test data as inputs provide easy setup of internal state esign strategies for test (design for testability): ad ad-hoc testing scan scan-based approaches self self-test and built-in in testing MicroLab, VLSI-23 (2/24)

3 Ad-hoc testing # Ad-hoc test techniques are a collection of ideas aimed at reducing the test time. Common techniques are: partitioning large sequential circuits adding test points adding multiplexers providing for easy state access co 3 3 co 2 2 test test load load co 3 3 co 2 2 test test test load load... co 3 3 co 2 2 co test load co test load co vdd co vdd test load co vdd test load co half-adder adder MicroLab, VLSI-23 (3/24)

4 Ad-hoc testing #2 bus oriented test technique bus unit unit 2 unit 3 unit 4 multiplexer based testing A inp B inp A control Module A Module B B control Module A Module B Module A Module B A out test test2 B out Module A test: {test,test2}={,} MicroLab, VLSI-23 (4/24)

5 Scan an-based test techniques # Idea: : have a in which all registers are chained into one giant shift register which can be loaded/ read-out bit serially. Test remaining (combinational) logic by () in test, shift in new values for all register bits thus setting up the inputs to the combinational logic (2) clock the circuit once in normal, latching the outputs of the combinational logic back into the registers (3) in test, shift out the values of all register bits and compare against expected results. One can shift in new test values at the same time (i.e., combine steps and 3). CL shift out shift in normal/test... normal/test scan-in normal/test scan-out MicroLab, VLSI-23 (5/24)

6 Scan-based test techniques #2 serial scan scan-out CL CL2 scan-in Scan registers serial scan chain partial serial scan: sometimes it is not area and speed efficient to implement scan in every location where a register is used (signal processing) R CL R4 CL CL R2 CL R5 R6 R3 MicroLab, VLSI-23 (6/24)

7 Level sensitive scan design A popular approach is the level sensitive scan design technique from T.W. Williams (LSS) the circuit is level sensitive (steady state response is independent of circuit and wire delays within a circuit): hazard free each register may be converted to a serial shift register C I A T B T 2 reg A reg B L L 2 C I A C I A B B Comb logic C I A C I A B B C I A B C I A B c shift- c serial data in shift data into reg A c2 normal operation shift reg B out serial data out shift- c2 MicroLab, VLSI-23 (7/24)

8 Scan Elements LSS C I A T B T 2 C I A L L 2 T B L 2 T 2 L scan FF TI TE TE b a TI TE TE a a b b b a MicroLab, VLSI-23 (8/24)

9 Self-Test Techniques: BILBO Problem: Scan-based approach is great for testing combinational logic but can be impractical when trying to test memory blocks, etc. because b of the number of separate test values required to get adequate fault f coverage. Solution: use on-chip circuitry to generate test data and check the results. Can be used at every power-on on to verify correct operation! circuit under test normal/test FSM A FSM B okay Generate pseudo-random data for most circuits by using, e.g., a linear feedback shift register (LFSR). Memory tests use more systematic FSMs to create AR and ATA patterns. For pseudo-random input data simply compute some hash of output values and compare against expected value ( signature ) at end of test. Memory data can be checked cycle-by by-cycle. MicroLab, VLSI-23 (9/24)

10 Linear Feedback Shift Register (LFSR) If C i s are not programmable, can eliminate AN gates and some XOR gates... c c 2 c c n- c n + m 2 3 n c x + c2x + c3x cn x + c n x n with a small number of XOR gates the cycle time is very fast. Cycle through fixed sequence of states (can be as long as 2 n - for some n s). Handy for large modulo-n counters. different responses for different initial states different responses for different c i pseudo-random sequence generator (PRSG) MicroLab, VLSI-23 (/24)

11 serial in Signature Analysis signature analysis is used to compact a data stream into a so called signature different responses for different c i, many well- known CRC (cyclic redundancy check) polynomials correspond to a specific choice of c s. i c c 2 c c n- c n parallel in c c 2 C n-.... z q z 2 q 2 z n- q n- z n q n MicroLab, VLSI-23 (/24)

12 LFSR Polynomials polynomials for maximal long sequences for n equal up to 32 n f(x),2,3,4,6,7,5,22 +x+x n 5,,2,29 +x 2 +x n,7,2,25,28,3 +x 3 +x n 9 +x 4 +x n 23 +x 5 +x n 8 +x 7 +x n 8 +x 2 +x 3 +x 4 +x n 2 +x+x 4 +x 6 +x n 3 +x+x 3 +x 4 +x n 4,6 +x 3 +x 4 +x 5 +x n 9,27 +x+x 2 +x 5 +x n 24 +x+x 2 +x 7 +x n 26 +x+x 2 +x 6 +x n 3 +x+x 2 +x +x n 32 +x+x 2 +x +x n examples of CRC s n CRC 8 +x+x 4 +x 5 +x 7 +x 8 6 +x 2 +x 5 +x 6 MicroLab, VLSI-23 (2/24)

13 BILBO # Very popular built-in in test structure is the built-in in logic block observation (BILBO) from Koenemann BILBO operate in 4 different s parallel register BILBO register normal operation of circuit BILBO register PRSG or signature analysis BILBO PRSG normal operation of circuit BILBO signature analysis scan BILBO scan normal operation of circuit BILBO scan reset BILBO reset normal operation of circuit BILBO reset MicroLab, VLSI-23 (3/24)

14 BILBO #2 example of a BILBO element with polynomials +x+x 4 c c scan in 2 3 scan out c c function A scan B reset C PRSG or signature analyzer parallel registers MicroLab, VLSI-23 (4/24)

15 I Testing A-me meter er (measures I ) V GN Idea: CMOS logic should draw no current when it s not switching. So after initializing circuit to eliminate tri-state fights, disable pseudo-nmos gates, etc., the power-supply current should be zero after all signals have settled. Good for detecting bridging faults (shorts). May want to try several different circuit states to ensure all parts of the chip have been observed. MicroLab, VLSI-23 (5/24)

16 System-Level Test: Boundary Scan The IEEE 49. boundary scan architecture provides a standardized serial scan path through the I/O pins of a chip (also called JTAG) at the board level, chips obeying the standard may be connected in a variety of series and parallel combinations for board testing (replacing bead of nails) standardized tests: connectivity tests between components sampling and setting chip I/Os distribution an collection of self-test or built-in in-test results PCB interconnect serial test interconnect IO pad and boundary cell serial data in MicroLab, VLSI-23 (6/24) serial data out

17 Boundary Scan: Test Access Port The test access port (TAP) is a definition of the interface that needs to be included in an IC TCK: test clock input TMS: test select TI: test date input TO: test data output TRST: optional signal for asynchronous reset the TAP the test architecture test data registers TI instruction decode instruction registers TO clocks/control TCK TMS (TRST) TAP controller MicroLab, VLSI-23 (7/24)

18 Boundary Scan: TAP controller State machine for the TAP controller. TMS is the control signal. test-logic reset run-test/idle select-r R-scan select-ir IR-scan capture-r capture-ir shift-r shift-ir exit-r exit-ir pause-r pause-ir exit2-r exit2-ir update-r update-ir MicroLab, VLSI-23 (8/24)

19 Boundary-scan: IR Instruction register (IR): minimum 2 bits data from last cell shiftir clockir to next IR bit updateir TRST reset IR bit FSM state capture-ir shift-ir exit-ir pause-ir exit2-ir update-ir shiftir clockir updateir MicroLab, VLSI-23 (9/24)

20 TAP data register (R) Boundary-scan: R boundary scan registers TI internal data register bypass register ( bit) TO boundary scan register is a special case of a data register. It allows circuit board interconnections to be tested, external components tested, and the state of the chip digital I/Os to be sampled. The boundary scan register is mandatory. internal data registers are optional and add additional access to the circuit. the bypass register is a bit register used to bypass a whole chip. MicroLab, VLSI-23 (2/24)

21 Boundary-scan: R boundary scan input and output cells in PA from chip last cell last cell shiftr clockr updater boundary scan bi-directional cell shiftr clockr next cell next cell updater to chip out PA enable from chip last cell to chip shiftr shiftr shiftr clockr clockr next cell clockr updater updater updater MicroLab, VLSI-23 (2/24) bidir PA

22 Boundary scan: instructions Minimum 3 instructions Bypass (all ): it is used to bypass any serial data registers in a chip with a bit register. This allows specific chips to be tested in a serial-scan scan chain without having to shift through the accumulated SR stages in all the chips Extest (all ): testing of off chip circuitry sample/preload: places the boundary scan registers (at the chips I/O pins) in the R chain, and samples or preloads the chips I/Os optional recommended instructions: Intest: : single-step step testing of internal circuitry via the boundary scan registers Runbist: run internal self-testing procedures within a chip MicroLab, VLSI-23 (22/24)

23 Coming Up... Next time: Top down design. Hardware description languages, logic synthesis. Readings Weste: 7.3 through (ad-hoc scan-based testing) through (BILBO) (Iddq testing) 7.5 (boundary scan) MicroLab, VLSI-23 (23/24)

24 Exercises: VLSI-22 Ex vlsi22. (difficulty: easy): calculate the pseudo- random sequence of an LFSR with the implemented polynomial +x+x 3 use the start value x Result:,3,7,6,5,2,4,,... MicroLab, VLSI-23 (24/24)