Basic Design Flow System design System/Architectural Design Instruction set for processor Hardware/software partition Memory, cache Logic design Logic Design Logic synthesis Logic optimization Technology mapping Physical design Physical Design/Layout Floorplanning Placement Routing Fabrication Logic Synthesis_Supp 1of 24 Design Cycles HDL System/Architectural Design Logic Design Verification/Simulation Physical Design/Layout Parasitic Extraction Fabrication Testing Logic Synthesis_Supp 2of 24 1
Design and Technology Styles Custom design Mostly manual design, long design cycle High performance, high volume Microprocessors, analog, leaf cells, IP Standard cell Pre-designed cells, CAD, short design cycle Medium performance, ASIC FPGA/PLD Pre-fabricated, fast automated design, low cost Prototyping, reconfigurable computing Logic Synthesis_Supp 3of 24 Synthesis Logic synthesis Boolean descriptions => circuits RTL synthesis RTL descriptions => Boolean descriptions Behavioral synthesis Behavioral descriptions => RTL descriptions Logic Synthesis_Supp 4of 24 2
Logic Synthesis Behavioral Descriptions Technology Libraries Translation Engine Optimization Engine Mapping Engine Two-level Logic Functions Optimized Multilevel Logic Functions Technology Implementation Logic Synthesis_Supp 5of 24 Translation Engine Read in HDL-based descriptions Translate into Boolean equations SOP sum of product POS product of sum A HDL description consisting only of a netlist of combinational primitives without feedback can always be synthesized Logic Synthesis_Supp 6of 24 3
Logic Optimization Remove redundant logic, exploit logic sharing Substitution Factoring Decomposition Extraction Elimination/flattening Logic Synthesis_Supp 7of 24 Substitution Express a Boolean function in terms of its inputs and another function G = a + b F = a + b + c G = a + b F = G + c Logic Synthesis_Supp 8of 24 4
Factoring Find the common factors among a set of functions F = ac + ad + bc + bd + e F = ( a + b ) ( c + d ) + e Two-level => multi-level Area reduced Delay increased Logic Synthesis_Supp 9of 24 Decomposition Express one Boolean function in terms of new nodes F = abc + abd + a c d + b c d 9 gates, 40 transistors F = XY + X Y X = ab Y = c + d 7 gates, 24 transistors Logic Synthesis_Supp 10 of 24 5
Extraction Express a set of Boolean functions in terms of new nodes F = ( a + b ) cd + e G = ( a + b ) e H = cde X = a + b Y = cd F = XY + e G = Xe H = Ye Logic Synthesis_Supp 11 of 24 Elimination / Flattening Remove a node in a function Increase area Reduce delay F = Ga + G b G = c + d F = ac + ad + bc d Logic Synthesis_Supp 12 of 24 6
Combinational Logic Delay clock Register Primary Input Combinational Logic Register Primary Output Combinational logic delay <= clock period Logic Synthesis_Supp 13 of 24 LOGIC SYNTHESIS DESIGN Original Network Logic Synthesis Logic Optimization Optimized Network Technology Mapping Optimized Circuit Logic Synthesis_Supp 14 of 24 7
K Map shows the relationship between inputs and outputs horizontally and vertically adjacent squares differ only in one variable CD Logic Synthesis_Supp 15 of 24 Looping :a process combining the squares which contain 1s. Looping can eliminate the variable that appears in complemented & uncomplemented form! Examples of looping pairs of adjacent 1s Logic Synthesis_Supp 16 of 24 8
Looping can eliminate the 2 variables that appear in both complemented & uncomplemented form! Examples of looping groups of four 1s (quads) Logic Synthesis_Supp 17 of 24 Looping can eliminate the 3 variables that appear in both complemented & uncomplemented form! Examples of looping groups of eight 1s (octets) Logic Synthesis_Supp 18 of 24 9
Complete Simplification Process Construct the K map, place 1s as indicated in the truth table. Loop 1s (not adjacent to any other 1s). Loop 1s (adjacent to only one other 1) that are in pairs. Loop 1s in octets even if they have already been looped. Loop quads that have one or more 1s not already looped. Loop any pairs necessary to include 1s not already looped. Form the OR sum of terms generated by each loop. Logic Synthesis_Supp 19 of 24 EXAMPLES Logic Synthesis_Supp 20 of 24 10
Don t-care Conditions are certain input conditions for which there are no specified output levels. Don t-care conditions should be changed to either 0 or 1 to produce K-map looping that yields the simplest expression. Logic Synthesis_Supp 21 of 24 REVIEW EXAMPLE Logic Synthesis_Supp 22 of 24 11
SUMMARY Compared to the algebraic method, the K-map process is a more orderly process requiring fewer steps and always producing a minimum expression. Logic Synthesis_Supp 23 of 24 More for Grad. Students 5-variable K-MapK Sum-of of-products minimization Exclusive-OR based K-MapK Logic Synthesis_Supp 24 of 24 12