LX5280. High-Performance RISC-DSP for IP Licensing

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1 High-Performance RISC-DSP for IP Licensing Bob Gelinas, Charlie Hauck, Pat Hays, Franklin Hooker, Kevin Joyce, Sol Katzman, Charley Lind, Elliot Mednick, Tat Ng, Jonah Probell, Sam Rosen, Bill Rubin Lexra, Inc.

2 Goal: Licensed RISC-DSP for SoC Designs LOW COST, LOW POWER in single-processor SoC designs 3URGXFWV*FHOOSKRQHV$'6/PRGHPV &KDOOHQJHHOLPLQDWHUHGXQGDQWVXEV\VWHPV HIGH PERFORMANCE in multi-channel SoC designs 3URGXFWVZLUHOHVVEDVHVWDWLRQV9R,3JDWHZD\V &KDOOHQJHVXSSRUWPXOWLSURFHVVRU,&V

3 Outline Architecture Instruction Set Program Development Implementation Summary

4 Architecture: Overview ICACHE ICACHE ICACHE CONTROL ICACHE CONTROL INST ADDR. INSTR A INSTR B ADDRESS RALU B RALU A COPROCESSOR Int Int SYSTEM I/F DATA OUT DATA IN DATA BUS DATA ADDR. CONTROL DUAL MAC CUSTOMER ENGINE DCACHE CONTROL COP[1-3] I/F A configurable processor subsystem for SoC design DSP extensions 6XSHUVFDODUVWDJHSLSHOLQH /RZRYHUKHDGLQWHUUXSWV 1HZLQVWUXFWLRQVGXDO0$& DCACHE CUSTOMER COPROCESSOR

5 Architecture: SIMD Multiply-Accumulate Dual 16-bit/32-bit MACs Pipelined for single-cycle 16-bit multiply-accumulate High-fidelity DSP arithmetic RSWLRQDOVDWXUDWH IUDFWLRQDODULWKPHWLFPRGH JXDUGELWV URXQGLQJ VXSSRUWIRUELWH[DFWWHOHFRPVWDQGDUGV 32 rx MULT 1 (16-bit) 32 ADD, SUB, RND 1 ry a0h(39) a1h(39) a2h(39) a3h(39) MULT 0 (16-bit) PROD 1 (32) PROD 0 (32) ADD, SUB, RND 0 a0l(39) a1l(39) a2l(39) a3l(39) Scaler >> [0-7] 16/32 Scaler >> [0-7] 16/32

6 Architecture: Bandwidth/Execution Balance Twinword Load/Stores of 32-bit general-register pairs sustain two (2) MACs/cycle DATA1(32) DATA0(32) Pipe B MADD am, rx, ry MADD am, rx, ry MADD am, rx, ry MADD am, rx, ry Pipe A LT reg, MEM LT reg, MEM LT reg, MEM LT reg, MEM MAC1 A0H-A3H 8P (4R/4W) REGISTER FILE MAC0 A0L-A3L

7 Instruction Set: DSP Extensions to MIPS NEW INSTRUCTION DESCRIPTION macop2[.s] am, rx, ry single or dual 16-bit (mult, madd, msub) single-cycle throughput optional saturate multop am, rx, ry 32-bit integer multiply [16-bit, 16-bit] complex multiply accop[.s] ad, as, at accumulator ops (add, sub) rnda2 am[, n] optional saturate (.s) mta2 rx, am optional alignment shift (n) mfa2 rx, am[, n]

8 Instruction Set: DSP Extensions (cont.) NEW INSTRUCTION DESCRIPTION aluop2[.s] rd, rs, rt dual 16-bit versions of all MIPS I ALU ops six new DSP ALU ops optional saturate (.s) loadop [.cn] rt, (pnt)stride postmodified pointers storeop [.cn] rt, (pnt)stride optional circular buffers (.cn) cmv[cond] rd, rs, rt conditional moves blcnzl rt, destination branch on loop count not zero, auto decrement

9 Program Development: RISC-DSP Tool Flow '63([WHQVLRQV 2SWLPL]H 6RXUFH )LOHV & 6RXUFH )LOHV $VVHPEO\ '63 6XSSRUW &RPSLOHU PHHWV FRQVWUDLQWV,QWHUPHGLDWH $VVHPEO\ '63 /LE /LQNHU /LEUDU\ )LOHV 1HZOLE 3021 /LE *UDSKLFDO 'HEXJJHU,663URILOLQJ 9HULORJ 6LPXODWRU (YDOXDWLRQ %RDUG (YDOXDWLRQ %RDUG,&( (-7$*

$Implementation: Licensing Model RTL (Available: Nov 99) 9HULORJVRXUFHFRGH &RQILJXUDWLRQWRROOFRQILJ 6\QWKHVLVDQGWLPLQJVFULSWV 7HVWDELOLW\VFULSWV 5HJUHVVLRQVXLWH SmoothCore (Available: Feb 00)$

10 Implementation: Licensing Model RTL (Available: Nov 99) 9HULORJVRXUFHFRGH &RQILJXUDWLRQWRROOFRQILJ 6\QWKHVLVDQGWLPLQJVFULSWV 7HVWDELOLW\VFULSWV 5HJUHVVLRQVXLWH SmoothCore (Available: Feb 00) *'6GDWDEDVH 9HULORJVLPXODWLRQPRGHOV 6\QWKHVLVDQGWLPLQJPRGHOV IDXOWFRYHUDJHYHFWRUV 5HJUHVVLRQVXLWH wire PI_STMODE_N = STMODE_N; wire PI_SIN = SIN; assign CCRhold assign CChold = PO_CCRhold; = PO_CChold; CLK) begin if (!RESET_D2_R_N) begin CFG_CEENBL_D1_R <= CFG_CEENBL; end end

11 Implementation: Technology POWER OPTIMIZED PERFORMANCE OPTIMIZED Technology Circuit Design 0.18µm CMOS 4-layer metal Single-edge, fully-static, standard cell 0.18µm CMOS 4-layer metal Single-edge, fully-static, standard cell Voltage 1.0 Volts 1.8 Volts System Clock 50 MHz 200 MHz Peak Performance 100 MMACs 400 MMACs Area (excludes RAMs) 5.5 mm 2 6 mm 2 Power (worst case) 20 mw 225 mw MMACs/mm mw/mhz

12 Implementation: Benchmarks Algorithm Cycles Example (200 MHz) Dot Product 0.84 µsec (2 vectors, length N) N + 8 (N = 256) Real FIR 10 µsec (N coefficients, (0.5N + 4) M (N = 32, M = 100) M samples) Complex FIR 34 µsec (N coefficients, (2N + 4) M (N = 32, M = 100) M samples) Complex FFT 179 µsec (N-point, radix-2) log 2 N (3.25N + 10) N + 40 (N = 1024)

13 Summary The /; has extended the scope of the MIPS architecture and tool chain into a wide range of DSP applications.

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