SIMD. 2.1 Computation Reuse [1] Memoization [2] Nagoya Institute of Technology. Nara Institute of Science and Technology

Transkript

1 SIMD 1 CPU [1] 1 Nagoya Institute of Technology 2 Nara Institute of Science and Technology Computation Reuse Memoization [2] c 2017 Information Processing Society of Japan 1

2 [3] Auto- Memoization Processor [1] call return ALU 1 D$1 2 D$2 MemoTbl Memoize engine MemoTbl MemoBuf MemoTbl MemoTbl MemoBuf MemoTbl MemoTbl MemoTbl MemoTbl MemoBuf MemoBuf MemoTbl MemoBuf 1 1 FLTbl Start Addr SP retofs ReadWrite FLTbl F or L addr FLTbl input values parent S (cycles) next addr read ec flag Ovh write OutTbl hit hist. InTbl AddrTbl OutTbl 1 for overhead filter FLTbl MemoTbl output addr output value next Read Write MemoBuf MemoBuf MemoBuf top MemoTbl 1 MemoTbl FLTbl InTbl AddrTbl OutTbl 4 FLTbl AddrTbl OutTbl RAM InTbl 3 CAM Content Addressable Memory FLTbl 1 1 F or L addr S Ovh read/write hit hist. InTbl FLTbl FLTbl input values parent input values 1 c 2017 Information Processing Society of Japan 2

3 AddrTbl InTbl 1 1 AddrTbl next addr ec flag OutTbl OutTbl OutTbl FLTbl FLTbl output addr output values next 2.2 MemoTbl MemoTbl FLTbl 1 hit hist T M T FLTbl S M (S Ovh R Ovh W ) (1) Ovh R Ovh W MemoTbl MemoTbl MemoTbl (T M) Ovh R (2) 1 Comparison (Register and CAM) Comparison (Cache and CAM) Write back (MemoTbl to Register) Write back (MemoTbl to Cache) D1 cache line size ways latency miss penalty D2 cache line size ways latency miss penalty Register windows miss penalty 9 cycles/32 Bytes 10 cycles/32 Bytes 2 cycle/32 Bytes 1 cycle/32 Bytes 32 KBytes 32 Bytes 4 ways 2 cycles 10 cycles 2 MBytes 32 Bytes 4 ways 10 cycles 100 cycles 4 sets 20 cycles/set Gain Gain = M (S Ovh W ) T Ovh R (3) Gain MemoTbl SPEC CPU95 SPARC V8 1 SPARC64-III[4] c 2017 Information Processing Society of Japan 3

4 ckbrkpts classify intswap checklmt ALL isspace output getcode puttype ALL mark xlevlist xlmatch xlygetvalue ALL (a) 124.m88ksim (b) 129.compress (c) 130.li memcpy write_ scan_ headr jcopy_ sample_ rows accsec_ virt_ sarray ALL str_sset safefree apush strchr ALL (d) 132.ijpeg (e) 134.perl 2 2 e 134.perl o cycle r ovh r cycle o cycle r ovh r cycle (B) str sset (R) (P) (B) safefree (R) (P) (B) apush (R) (P) (B) strchr (R) (P) (B) (R) (P) (B) (R) (P) 4 (B) (B) (P) 2 2 e 134.perl o cycle r ovh (r cycle) (R) (P) e str sset 2 str sset (B) (P) (B) (P) r cycle str sset c 2017 Information Processing Society of Japan 4

5 3 e 134.perl str sset (B) d25c a c eb (R) 29fa e9e bf ec d c c cc a f (P) 2a71c eb4c efdc c (B) (R) str sset (P) (P) (B) 3 3 (B) (P) 1d284 26a00 2a71c 2eb4c (B) (P) (B) o cycle (B) r ovh r cycle 2 e str sset 2 str sset (R) (P) (R) o cycle (P) 3 (P) 2eb4c 2efdc 3 (P) (R) 2e9e0 2efdc 2eb4c 2efdc 2e9e0 2efdc str sset (R) 2eb4c 2efdc (P) 2efdc (R) (P) o cycle 2 e str sset 2 str sset (B) (R) (R) (B) (R) 2eb4c r ovh r cycle 2 e strchr B r ovh B 4. r ovh c 2017 Information Processing Society of Japan 5

6 4 (B) (R) (P) 124.m88ksim compress li ijpeg perl FLTbl1 FL1 FLTbl2 F or L S (cycles) addr read Ovh paddr write #1 #n hit hist. paddr paddr 4 4 (P) 629 (R) 403. FLTbl InTbl FLTbl FLTbl FLTbl InTbl FLTbl 1 1 FLTbl1 FLTbl2 InTbl FLTbl1 FLTbl1 FLTbl2 FLTbl RAM FLTbl1 FLTbl2 3 FLTbl1 FL1 FLTbl 3 FLTbl FLTbl2 paddr FLTbl2 FLTbl2 FLTbl2 FLTbl2 FLTbl 5. [1] Tsumura, T., Suzuki, I., Ikeuchi, Y., Matsuo, H., Nakashima, H. and Nakashima, Y.: Design and Evaluation of an Auto-Memoization Processor, Proc. Parallel and Distributed Computing and Networks, pp (2007). [2] Norvig, P.: Paradigms of Artificial Intelligence Programming, Morgan Kaufmann (1992). [3] Huang, J. and Lilja, D. J.: Exploiting Basic Block Value Locality with Block Reuse, Proc. 5th Int l Symp. on High-Performance Computer Architecture (HPCA- 5), pp (1999). [4] HAL Computer Systems/Fujitsu: SPARC64-III User s Guide (1998). c 2017 Information Processing Society of Japan 6